In the design and manufacture of semiconductor IC chip packages and modules (e.g., SCM (single chip modules), MCMs (multi-chip modules), etc.), it is imperative to implement mechanisms that can effectively remove heat generated by IC chips, such as microprocessors or other high-performance chips, to ensure continued reliable operation of the IC chips. Effective heat removal becomes increasingly problematic as chip geometries are scaled down and operating speeds are increased, which results in increased power density. Moreover, as chip packages or electronic modules become more compact with multiple IC chips densely packed together, the increased heat density generated by operation of the chips in such close proximity can adversely affect integrated circuit components and cause physical damage to the package structure due to differences in thermal expansion of the package components. Accordingly, there is a continuing need for improved devices and methods for effectively cooling high-density and/or high-performance IC chip packages and modules.
One method of dense packaging of high performance chips, known as “system on a package”, uses a silicon carrier with electrical through vias as an additional intermediate package layer between the chips and a ceramic first level package to provide high density and high performance electrical interconnects, such as described in U.S. Pat. No. 6,593,644, entitled “System on a Package Fabricated on a Semiconductor or Dielectric Wafer with Wiring on One Face, Vias Extending Through the Wafer, and External Connections on the Opposing Face,” which is commonly assigned and fully incorporated herein by reference. Packaging structures and method described in this patent provide a number of significant advantages, but one critical factor that should be considered for practical implementations of package structures with silicon carriers is the size and thickness of such silicon carriers. For a silicon carrier to be useful, the carrier should be larger in size than the size of the chip or chip array to be mounted on the carrier. For example, the largest practical size for a high performance chip is currently about 20 mm×20 mm. Therefore, to mount a 2×2 array of such chips, the silicon carrier would need to be over 40 mm×40 mm in size.
Another factor that is considered when using silicon carriers in package structures is the thickness of the silicon carrier. It is desirable to make the silicon carrier substrate as thin as possible due the difficulties associated with forming electrical through vias and filling the vias with a conductive material and minimizing the inductance of the electrical interconnects. For example, if a silicon carrier is 0.2 mm thick and 40 mm wide, the width/thickness ratio is 200:1. As reported in the literature, a practical silicon carrier thickness is primarily limited by the ultimate aspect ratio of the through vias. In general, aspect ratio values much higher than about 10:1 are considered to be difficult to manufacture and make highly reliable. By way of example, the consortium composed mainly of Japanese Electronics companies known as the Association of Super-Advanced Electronic Technologies (ASET) has worked intensively on silicon carrier through-via technology for the past five years (see Takahasi, K. et al., “Current Status of Research and Development of Three-dimensional Chip Stacking Technology”, Jpn. J. Appl. Phys. Vol. 40, (2001) pp. 3032-3037), and such work has culminated in a reportedly robust process employing 10 um wide vias and a carrier thickness fixed at 50 um (see Takahashi, K. et al., “Process Integration of 3D Chip Stack with Vertical Interconnection”, Proc. 54th Electron. Components and Technol. Conf. Las Vegas, Nev., June 2004, pp. 601-609).
Some of the practical difficulties which occur with a large area and thin silicon carrier include increased risk of fracturing the silicon carrier during processing, bonding or assembly, as well as providing an effective means for cooling the chips mounted on the silicon carrier. It is difficult to use a conventional cooling means such as a thermal paste layer and a heat sink attached to the back surface of the chips since the force used to hold the heat sink in place and the large force used during assembly to insure a thin and uniform thermal paste layer could crack the silicon carrier. Therefore, packaging structures and methods that provide increased stiffness of a silicon carrier while providing a high performance cooling solution are highly desirable.